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Design of Low-Power Coarse-Grained Reconfigurable Architectures - Paperback

$166.84 USD
$166.84 USD
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Design of Low-Power Coarse-Grained Reconfigurable Architectures - Paperback
Design of Low-Power Coarse-Grained Reconfigurable Architectures - Paperback
Design of Low-Power Coarse-Grained Reconfigurable Architectures - Paperback
$166.84/ea
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Product Description

by Yoonjin Kim (Author), Rabi N. Mahapatra (Author)

Coarse-grained reconfigurable architecture has emerged as a solution for flexible, application-specific optimization of embedded systems. Helping you understand the issues involved in designing and constructing embedded systems, this book offers new frameworks for optimizing the architecture of components in embedded systems in order to decrease area and save power. Real application benchmarks and gate-level simulations substantiate these frameworks. The first half of the text explains how to reduce power in the configuration cache. The second half focuses on the design of a cost-effective processing element array to reduce area and power consumption.

Author Biography

Yoonjin Kim is an assistant professor in the Department of Computer Science at Sookmyung Women's University in Seoul, South Korea. Dr. Kim was previously a senior R&D staff member at Samsung Advanced Institute of Technology in Yongin, South Korea. He earned his Ph.D. in computer engineering from Texas A&M University. His research interests include embedded systems, computer architecture, VLSI/system-on-chip design, and hardware/software co-design.

Rabi N. Mahapatra is a professor in the Department of Computer Science and Engineering and director of the Embedded Systems and Codesign Laboratory at Texas A&M University in College Station. He is an associate editor of the ACM Transactions on Embedded Computing and an editorial board member of the International Journal on Information and Communication Technology. Dr. Mahapatra is also founder and chairman of the Bhubaneswar Institute of Technology (BIT) in India. His research interests include network on chip, system-on-chip reliability, low-power IP lookup architectures, and intention-based searching.

Number of Pages: 224
Dimensions: 0.6 x 9.2 x 6.1 IN
Illustrated: Yes
Publication Date: June 14, 2017
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