Product Description
by Pallavi Srivastava (Author)
This book is intended for designers with experience in traditional (clocked) circuit design, seeking information about asynchronous circuit design, in order to determine if it would be advantageous to adopt asynchronous methodologies in their next design project. The author introduces a generic approach for implementing a deterministic completion detection scheme for asynchronous bundled data circuits that incorporates a data-dependent computational process, taking advantage of the average-case delay. The author validates the architecture using a barrel shifter, as shifting is the basic operation required by all the processors. The generic architecture proposed in this book for a deterministic completion detection scheme for bundled data circuits will facilitate researchers in considering the asynchronous design style for developing digital circuits.
Back Jacket
This book is intended for designers with experience in traditional (clocked) circuit design, seeking information about asynchronous circuit design, in order to determine if it would be advantageous to adopt asynchronous methodologies in their next design project. The author introduces a generic approach for implementing a deterministic completion detection scheme for asynchronous bundled data circuits that incorporates a data-dependent computational process, taking advantage of the average-case delay. The author validates the architecture using a barrel shifter, as shifting is the basic operation required by all the processors. The generic architecture proposed in this book for a deterministic completion detection scheme for bundled data circuits will facilitate researchers in considering the asynchronous design style for developing digital circuits.
- Analyzes circuit design techniques in the context of timing constraints;
- Develops a generic, deterministic completion detection scheme for asynchronous circuits using bundled data protocol;
- Demonstrates a single-precision, asynchronous bundled data barrel shifter to validate the completion detection scheme.
Author Biography
Pallavi Srivastava holds a Ph.D. in Electronics Engineering from Taylor's University, Malaysia (2022). She is an innovative and passionate educator having nine years of experience in industry and academics. She received her Master of Technology in Control Systems from VJTI, Mumbai, India (2012), and Bachelor of Technology in Electronics and Communication Engineering from Uttar Pradesh Technical University, India (2009), both with first-class honors. Her Master's dissertation was focused on designing an observer for Quantum Systems using Contraction Theory which is a recently developed nonlinear control system tool. Her research work also includes the design of fractional order controllers for robotic manipulators. She has authored papers in peer-reviewed journals and international conferences. Currently, Pallavi is working on the asynchronous design of digital circuits and its application. More precisely, she is working towards developing a deterministic completion detection scheme for single-rail asynchronous circuits.
